Accelerating RISC

ICDesign
2023-09-23 23:01:15

In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are predominantly heterogeneous but occasionally homogeneous.

A recent trend is the widespread adoption of RISC-V cores, which are built upon open standard RISC-V instruction set architecture (ISA). This system is available through royalty-free open-source licenses.

Here, the utilization of network-on-chip (NoC) technologies’ plug-and-play capabilities has emerged as an effective strategy to accelerate the integration of RISC-V-based systems. This approach facilitates seamless connections between processor cores or clusters and intellectual property (IP) blocks from multiple vendors.

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Network-on-chip basics

Using a NoC interconnect IP offers several advantages. The NoC can extend across the whole device, with each IP having one or more interfaces that span the entire SoC. These interfaces have their own data widths, operate at varying clock frequencies, and utilize diverse protocols such as OCP, APB, AHB, AXI, STBus, and DTL commonly adopted by SoC designers. Each of these interfaces links to a corresponding network interface unit (NIU), also referred to as a socket.

The NIU’s role is to receive data from a transmitting IP and then organize and serialize this data into a standardized format suitable for network transmission. Multiple packets can be in transit simultaneously. Upon arrival at its destination, the associated socket performs the reverse action by deserializing and undoing the packetization before presenting the data to the relevant IP. This process is done in accordance with the protocol and interface specifications linked to that particular IP.

A straightforward illustration of IP blocks could be visualized as solid logic blocks. Additionally, an SoC usually utilizes a single NoC. Figure 1 illustrates a basic NoC configuration.

Figure 1 A very simple NoC representation shows basic design configuration. Source: Arteris

The NoC itself can be implemented using a variety of topologies, including 1D star, 1D ring, 1D tree, 2D mesh, 2D torus and full mesh, as illustrated in Figure 2.

Figure 2 The above examples show a variety of NoC topologies. Source: Arteris

Some SoC design teams may want to develop their own proprietary NoCs, a process that is resource- and time-intensive. This approach requires teams of several specialized engineers to work for two or more years. To make matters more challenging, designers often invest nearly as much time debugging and verifying an in-house developed NoC as they do for the rest of the entire design.

As design cycles shorten and time-to-revenue pressures increase, SoC development teams are considering commercially available NoC IP. This IP enables the customization required in an internally developed NoC IP but is available from third-party vendors.

Another challenge of the growing SoC complexity is the practice of utilizing multiple NoCs and various NoC topologies within a single device (Figure 3). For instance, one section of the chip might adopt a hierarchical tree topology, while another area could opt for a 2D mesh configuration.

Figure 3 The illustration highlights sub-system blocks with internal NoCs. Source: Arteris

In many cases, the IP blocks in today’s SoCs are the equivalent of entire SoCs of only a few years ago, making them sub-systems. Thus, the creators of these sub-system blocks will often choose to employ industry-standard NoC IP provided by a third-party vendor.

In instances requiring high levels of customizability and co-optimization of compute and data transport, such as a processor cluster or a neural network accelerator, the IP development team may opt for a custom implementation of the transport mechanisms. Alternatively, they might decide to utilize one of the lesser adopted, highly specialized protocols to achieve their design goals.

RISC-V and NoC integration

For a standalone RISC-V processor core, these IPs are available with AXI interfaces for designers who don’t need coherency and CHI interfaces for those who do. This allows these cores to plug-and-play with an industry-standard NoC at the SoC level.

Likewise, if design teams select one of the less commonly adopted protocols for inter-cluster communication in a RISC-V design, that cluster can also feature ACE, AXI or CHI interfaces toward external connections. This method allows for quick connection to the SoC’s NoC.

Figure 4 below features both non-coherent and cache coherent options. Besides their usage in IPs and SoCs, these NoCs can also function as super NoCs within multi-die systems.

Figure 4 A NoC interconnect IP is shown in the context of a multi-die system. Source: Arteris

NoC IP in RISC-V processors

The industry is experiencing a dramatic upsurge in SoC designs featuring processor cores and clusters based on the open standard RISC-V instruction set architecture.

The development and adoption of RISC-V-based systems, including multi-die systems, can be accelerated by leveraging the plug-and-play capabilities offered by NoC technologies. This enables quick, seamless and efficient connections between RISC-V processor cores or clusters and IP functional blocks provided by multiple vendors.

Frank Schirrmeister, VP solutions and business development at Arteris, leads activities in the automotive, data center, 5G/6G communications, mobile, aerospace and data center industry verticals. Before Arteris, Frank held various senior leadership positions at Cadence Design Systems, Synopsys and Imperas, focusing on product marketing and management, solutions, strategic ecosystem partner initiatives and customer engagement.