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Chiplet interconnect handles 40 Gbps/bump

Eliyan announced the first silicon implementation of its NuLink PHY chiplet interconnect, operating at 40 Gbps/bump to enable a beachfront bandwidth of 2.2 Tbps/mm. Fabricated on TSMC’s 5-nm process node, the NuLink chip uses standard organic packaging with a 130-µm bump pitch. With finer bump pitches, the bump-limited NuLink PHY can deliver as much as 3 Tbps/mm.

The successful silicon implementation of NuLink technology demonstrates that it can be applied in organic substrate packaging to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations that employ advanced packaging technologies. For example, NuLink eliminates the need for silicon interposers (in most applications) that limit overall system-in-package (SiP) size and ultimately constrain performance. Without the drawbacks of advanced packaging, the NuLink chiplet interconnect allows a greater number of cores and compute performance per power at lower cost and higher yield.

NuLink technology is the foundation of the Bunch of Wires (BoW) standard adopted by the Open Compute Project and is compatible with the Universal Chiplet Interconnect Express (UCIe) standard. Eliyan is currently working with standards bodies to create an efficient universal die-to-die interconnect optimized for memory traffic to help accelerate the adoption of memory chiplets.

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Silicon characterization data is available now. Eliyan is also in the process of porting its design to multiple foundry and node technologies based on early customer interest and demand.


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