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Shannon decoder DAC meets UART

If you need to quickly and inexpensively convert a binary number into a proportional analog voltage, one cool (and easily remoted) way to do it is:

Serialize the number into a bit stream with the LSB output first,input the resulting stream into an RC time constant withRC = T/ln(2) where T = the inter-bit interval, andcapture the final integrated voltage at the end of bit string input with a S&H.

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This method is conceptualized as the Shannon decoder DAC (SDD) in Figure 1.

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Figure 1: The Shannon decoder DAC (SDD) concept.

Applying the SDD concept to implementation of a DAC (or multiple DACs) benefits from some useful facts.

Serializing and outputting binary numbers with LSB first is exactly what the standard universal asynchronous receiver/transmitter function (UART) does, andUARTs are widely and inexpensively available, both as USB-driven external RS232 peripherals for PCs (typically using the popular FDTI or similar chipsets and available fully cabled and connectorized for less than $10) and as internal peripherals in popular microcontroller chips (the TM4C123x contains eight!).

Figure 2 illustrates an SDD for 5-volt asynchronous serial data of the sort a µC UART might output, and Figure 3 is its timing diagram. Here’s how it works.

Figure 2 The SDD with 5V asynchronous serial data, similar to a µC UART output.

Figure 3 The SDD conversion cycle timing for 5V logic levels.

Serial transmission of bytes (at T = 8.68 µs = 115200 baud) for DA conversion follows standard UART formatting and begins with a ‘0’ start bit. This triggers the U2 555 timer via U1a and starts a (R2 + R3)C3 ln(3) = 78.1µs = 9T conversion cycle, driving U1b to isolate the C2 hold capacitor (which holds the previous conversion result) and connect the C1 sample capacitor to the R1 input integration resistor. Notice that

R1C1 = (R1 + Ron(U1c + U1b))C1 = (12400 + 140).001 µF = 12.54 µs = 8.69 µs/ln(2) is essentially identical to the theoretical Shannon time constant of T/ln(2), and differs from the ideal by only 0.13%, assuming nominal component values.

The U1c switch converts logic levels to U4’s reference levels and applies the resulting precision 0/+5.0V bitstream to R1C1. The conversion process continues for

8T = 69.4 µs. U2 then times out, driving CNV low, causing U1b to transfer the accumulated conversion result charge on C1 to C2 and from there to U3’s voltage follower unity-gain output.

U2 then resets, arming the circuit to respond to the next data input cycle when the next start bit arrives, completing the 10T = 86.8 µs = 1/11.52 kHz ripple-free conversion cycle. Higher baud rates and even faster conversion times are also easily possible.

Bipolar RS232 signaling, with its superior noise immunity, can also be easily accommodated by a different configuration of the U1a and U1c interface switches, as shown in Figure 4.

Figure 4: The SDD input modified for RS232 signal levels and polarity.

Figure 5 shows the resulting revised conversion timing.

Figure 5: The SDD analog conversion from RS232 signal levels.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. In all, a total of 64 submissions have been accepted since his first contribution was published in 1974.

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